SMIC's newest 7nm process nears TSMC density without EUV

An analysis of SMIC's third-generation N+3 process found it achieves a smaller metal pitch than Intel's 18A and transistor density comparable to TSMC's N6 node, all without EUV lithography. The process still falls short of modern nodes on performance and power efficiency.

Why it matters: It shows Chinese chipmakers continuing to close the fabrication gap using multi-patterning DUV workarounds despite export controls blocking EUV tool access. That matters for how long US chip sanctions can realistically slow the domestic silicon China builds for AI training.